Design of High Performance Parallel Multiplication using FPGA

Design of High Performance Parallel Multiplication using FPGA Jenila R Supraja C Dharani N Electronics and Communication Electronics and Communication Electronics and Communication Vel Tech Rangarajan Dr Sagunthala R&D Vel Tech Rangarajan Dr Sagunthala R&D Vel Tech Rangarajan Dr Sagunthala R&D Institute of Science and Technolgy, Institute of Science and Technolgy, Institute of Science and Technolgy, Chennai, India Chennai, India Chennai, India jenilarusel@gmail.com Dinesh Kumar V 2022 IEEE International Conference on Current Development in Engineering and Technology (CCET) | 978-1-6654-5415-5/22/$31.00 ©2022 IEEE Electronics and Communication Vel Tech Rangarajan Dr Sagunthala R&D Institute of Science and Technolgy, Chennai, India dinesh951dk@gmail.com Abstract - In the recent decade, decimal arithmetic has [5]. The operation requires a series of addition operations to received a lot of attention. In existing research on decimal be completed. As a result, the addition procedure can be multiplication, latency and area are two key factors.In any case, completed fast. The addition of multiple components to a today’s computerized frameworks and DSP applications; multiplier design is required. It could be the result of a Ripple energy/power utilization is a pivotal thought.For quick DSP, Effect. The carry save-ahead adder helps speed up carry low power and high speed multipliers are required. Because of its regular structure and ease of design, the array multiplier is computation [6-12]. one of the fastest multipliers. To boost multiplier speed and Paliwalet al [13] projects a differentiate research on two improve power dissipation with the least amount of delay, parallel & thrice parallel high speed FIR architecture for adders and CMOS power gating based CLA are employed. In twenty-four & seventy-two taps utilizing several adders and the paired number framework, the significant issue in number- multipliers Various adders are analyzed in such a manner that crunching relates to convey. A higher rad-ix number can be easy to select the suitable designs for different works. framework, Quaternary Signed Digit (QSD), is utilized to Simulations results were analysed to obtain power perform number juggling tasks without convey. consumption, area occupied and delay. From the results, it is concluded that traditional designs has maximum area usage Keywords— DSP, multiplier, low power, high speed, adders compared to the latest design which uses Han-Carlson adder based Vedic multiplier along with CSA. A low power and I. INTRODUCTION space efficient carry select adder is projected in [14][15][16] to generate half sum from half carry that reduces the usage of In computer frameworks, decimal augmentation is a basic XOR gate at each digit. Simulation result indicates 53.43% event. Decimal multiplication is most commonly used in increase in Area-Delay Product (ADP), 46.04% in Power- arithmetic units in various applications. Because decimal Delay Product (PDP) in comparison with the common multiplication contains a substantially larger number of Boolean logic (CBL) cum CSLA and for various bit-widths, digits, it is more difficult to understand than binary a mean power of 57.24% compare to conventional CSLA, multiplication. Multiplication by decimals is a difficult task, 44.29% compare to BEC-CSLA, 19.25 % compare CBL- resource-intensive, and time-consuming job. As a result, CSLA and 34.12% in comparison with SCG-CSLA. iterative techniques have been used in certain contemporary A 32 bit carry look ahead adder (CLA) is implemented CPU's [1]. using 8 block of 4-bit CLA, is distinguished with an available However, there are a few potential areas where parallel carry look ahead adder in [17] based on power and delay. It decimal multiplication Algorithms can be used in hardware. has been synthesized and simulated using cadence virtuoso During the process, they usually loop via multiplier, adding tool of 45 (nanometer) technologies at 1Volt power supply. the multiplicand bits to a register. In addition, while there has This can be used in DSP applications and the results indicated been various parallel decimal multiplication methods the lower error in comparison with the existing approximate reported, the main stream is considered were timer and area. CLA adder. The given work has mean power reduction of Though it is engaging for every circuit, it is most important 25% and 61% of less delay as compared to the available to be considered for energy/power consumption [2][3]. Since random designs & also when compared with conventional decimal calculations are hard to find in numerous essential CLA, the power reduction is 63% and 42% less delay. applications, for example, logical, modern, financial, and Saeidet al., [18] projected a 2-D decimal array multiplier Web applications, logical disciplines are interested in designs for traditional binary coded decimal operands. Here developing and executing decimal arithmetic data [4]. the partial products are generated by two ways: one method In most Digital Signal Processing applications, is based on selecting the partial products from pre-computed multiplication is a significant unit operation. The multiplier usual multiply of the multiplicand and the other method is the speed of a processor determines the speed of a digital signal generation of partial products through binary coded decimal processor. Designing an effective multiplier can help digit multiplier cells. The latter part shows 4% improvement complex DSP’S and microprocessor systems perform better Authorized licensed use limited to: VIT University. Downloaded on September 25,2023 at 16:24:58 UTC from IEEE Xplore. Restrictions apply. in the pipeline clock cycle. Also, the regularity & high clock frequency is achieved at 0.5 % area cost. The importance of decimal multiplication in arithmetic operations is elaborated in [19]. HDL Synthesis and timing analysis performed under 90 nm technology and the overall result is 11 % less delay compared to existing fast multiplier method. Modified booth multiplier, array multiplier, and binary multiplier, Wallace tree multiplier are the different types of multipliers [20][21]. Every multiplier contains a variety of structures and design. The performance Fig. 1. Array Multiplier requirements of multipliers make their implementation a difficult challenge. In this work, a Quaternary Signed Digit (QSD) decimal parallel multiplication method is proposed. An array of four AND gates is necessary for the The results are evaluated based on power dissipation, area aforementioned multiplication to generate the partial and delay using Xilinx Vivado latest version tool in Verilog products. In order to obtain the Resultant product, it is need HDL and compared with the existing array multipliers. to calculate the sum of partial product and its carry obtained The surviving paper is arranged as follows - In Section II by summing it. These are obtained from adder array. The P0, Introduction to array multiplier is elaborated with necessary P1, P2, P3 is obtained by column wise addition logic from diagrams. Section III explains the proposed QSD block A0, A1, B0, B1. For obtaining P (Partial Product), the Bits diagram and its methodology. Section IV gives the A0 and B0 are multiplied and reflect 0 it A0 is 1 and B0 is 0 simulation results with comparison parameters and Section and so on. This can be done by AND gate and followed by V listed the conclusion and future scope. OR gate for resultant product. Multiplication uses several adders that lead to power dissipation. This high excess power II. BASICS OF ARRAY MULTIPLIER can be solved by exploring and using better adder designs. An array multiplier [7] is a computational cascaded To make the first partial product, two AND gates are machine that produces an assemblage of full adders and half needed. Multiplying A1 by B1B0 and shifting it to the left adders multiple product search results engaged almost at the one position yields the second partial product. From the same time. For generating the product every time before the above calculation, the two half adders are combined for adder array, an array of gates is equipped [8][9]. Sequential adding the Bits in the vertical order as shown in figure 2. In processes requiring a sequence of add and shift micro- most circumstances, partial products have more bits than operations is checking the multiplier's bits one by one and whole products, necessitating the use of full-adders to producing partial products. In a single micro-operation, a compute the total. Because the least important bit of the combinational circuit that creates the result bits all at once product is produced by the output of the first AND gate, it can be used to multiply two binary values [10]. does not need to travel via an adder block. To form the multiplication array, every time the signal needs to propagate through the gates [11]. Though it is a frequent way, it is equipped rapidly for multiple processes. On the other side, this array multiplier will quest for a large number of gates. Until it formed as an integrated circuit, this will increase the cost. To make an array multiplier with a combinational circuit, multiply two 2-bit values. The main advantage of array multiplier is its simplicity and also regularity in shape [12]. But the delay and power consumption will be high compared to other multipliers. Proper design of adders will reduce more power and delay. Figure 1 denotes the array multiplier structure. Fig. 2. Column wise addition logic The Bit (multiplicand) pieces are A1 and A0, the another Bit (multiplier) pieces are B1 and B0, and the Bit is In a [8] similar way, a bit multiplication with additional Assumes the following binary digits can be made using the combination circuit. Each P1 = A0B0, P2 = A1B0, P3 = A0B1, P4 = A1B1 digit of a multiplier is multiplied with the every other bit in where, R is resultant product generated, c will be carry another input as many levels depend on the input. Each level generated by the resultant binary, of AND gates produce a new partial product by adding the P is partial product generated binary output in parallel with the preceding level's partial Step 1: R0 = A0B0 product. The final phrase is obtained directly for the first and Step 2: R1 = A1B0+A1B1 last bit from the first and first and the last column because, it Step 3: R3 = A1B1+c1 (c1 is carry generated from R1) has only one bit. Other bits were propagated through the OR Step 4: R4 = c2 (c2 is carry generated from R2) gates. A. Half Adder Authorized licensed use limited to: VIT University. Downloaded on September 25,2023 at 16:24:58 UTC from IEEE Xplore. Restrictions apply. To add two bits, a half adder combination circuit is TABLE I. FULL ADDER TRUTH TABLE needed. The two input bits are named as G and D are combined and addend, whereas the product bits are named as H-S (Sum) and H-C (Carry) shown in figure 3. Rather than usual basic gates, it is possible to build adders using multiplexer. This multiplexer permits us some Bit information that is 0 or 1 from some input Bits by combining them into a one bit line. Adders and multiplexers are two different logics. But, this can be performed with the standard cell library. III. PROPOSED METHODOLOGY In order to generate the appropriate output, the integer numbers must go through 3 phases shown in figure 5. Partial Product Generation (PPG), Partial Product Accumulation (PPA), and Final Output (Viewed in Xilinx Vivado Design Suite). Fig. 3. Half Adder and Truth Table Logical Expression: For H-S = G XOR D For H-C = G AND D Multiplication adds a carry from the lower order bits, because the half adder only has two inputs. B. Full Adder The full adder accepts has three inputs and generates two outputs. The first two entries are named X and Y, and the product is named F-IN. F-OUT denotes the carry output, whereas S denotes the ordinary output. The carry bit is cascaded from one adder to the next in a complete adder logic, which takes eight inputs and combines them into a byte-wide adder. Full adder is functional building block of microprocessors, digital signal processors and other ALU’s. Here FA (Full Adder) consists of gates similar to (HA) Half Fig. 5. Simulation Process Adder (or we can use two HA modules in FA) connected together, where carry of the first half adder (HA1) is 1) Partial Product Generation (PPG) forwarded to the second half adder (HA2). Figure 4 and table I. demonstrates full adder. The first stage entails obtaining two eight-digit integer Mathematical Expression for values. The first input will be An, and the second will be Bn. SUM: = G' D' F-IN + G' D F-IN' + G D' F-IN' + G D F-IN The number of binary digits in the binary digits is indicated = F-IN (G' D' + G D) + F-IN' (G' D + G D') = F-IN by "n." Despite the fact that decimals cannot be handled, the XOR (G XOR D) = (1, 2, 4, 7) decimal we entered into the Xilinx Vivado Design Suite translates to binary digits. We were generating partial products utilizing this procedure. As indicated in the diagram. 2) Partial Product Accumulation (PPA) After the post-processing is finished, the final products are generated column-by-column. This indicates that after each partial product is calculated by each integer, the next bit for the final product is calculated. As a result, after completing half of the calculation, the calculated data generates half of the ultimate product. The Fig. 4. Full Adder final output as demonstrated in the outline underneath. Full Adder Logical Expression for 3) Final Product C-OUT: = G' D F-IN + G D' F-IN + G D F-IN' + G D F-IN Final product is generated after the remaining bits are = G D + G D F-IN + G F-IN = (3, 5, 6, 7) completed. The finished result is created and displayed on the Xilinx Vivado Design Suite's unnamed tab. It can be seen Authorized licensed use limited to: VIT University. Downloaded on September 25,2023 at 16:24:58 UTC from IEEE Xplore. Restrictions apply. in a variety of formats, including unsigned integer, signed integer, decimal, binary, and hexadecimal. A. Pen And Paper Method Fig. 7. 4x4 Multiplications In this example a 4 bit binary digit is multiplied with another 4 bit binary digit. As a first step we are going to calculate the partial products so that we can proceed with the Column wise addition process. After generating the partial Fig. 6. Pen and Paper method for N-bit multiplication products the first column will consist of one bit data that is directly assigned to the last bit of the result. The second In this pen and paper method figure 6, with a clear idea column of the partial products consists of two binary bits it of how the whole process is carried out is explained. There is added using half-adder and it is assigned to R1. The next are two input from user that is A and B, The number of bits column will consist of 3 binary bits and a carry from the is denoted by n. where, K is this total bits and k-1 indicates result R1. Likewise the same procedure will be followed up the last bit. to the last column of the partial products. At last a carry will Because the first bit is accounted as 0 so that the last bit be remaining alone that is directly assigned to the first bit of will be n-k. S is the sum and C is the carry. After getting the the result. In this case that excess carry is directly assigned input as a first step each and every bit of the second input is to R7. multiplied with all the bits of the first input. This is the first By this procedure after completing the partial column which contains W0 that is directly assigned to the products calculation we will be having the half of the result result and the fourth coming columns and viper with the full part so that the overall time consumption will be reduced location or half location relying upon the number of pieces it that comprises in it. IV. EXPERIMENTAL RESULTS Upcoming columns and viper with the full location or half location relying upon the number of pieces it that comprises in and this call my tryout will be conveyed close by when these halfway items is generating so that the time development is decreased in the wake of ascertaining the fractional items will have the portion of the outcome. After that the remaining part of the result is to be generated. B. Algorithm Step 1: Start Step 2: Generate the partial products by traditional multiplication method denoted by variables An and Bn. If n=4, (A3, A2, A1, A0) & (B3, B2, B1, B0) Step 3: Produce partial products by using different adder circuits. Step 4: Generate the final product after post-processing using BCD codes. The final sum will be added with the n-bit binary coded decimal output to generate the original output. Step 5: Stop Fig. 8. 4 Bit Multiplication in Xilinx Vivado Above results shows the one bit decimal multiplier For example, Figure 7 denotes the 4x4 multiplication. simulated in Xilinx Vivado. Authorized licensed use limited to: VIT University. Downloaded on September 25,2023 at 16:24:58 UTC from IEEE Xplore. Restrictions apply. TABLE II. COMPARISON TABLE [11] Proposed Total on chip power 54.31 51.271mw LUT 200 197 Delay 53.45 52.34 The above (TABLE II) comparison table source that the proposed method is faster and less power construction in the overall execution of the full process and total power is reduced and the steps this method adopts column wise addition so that the number of half adders and the full address present in the overall execution is also reduced as shown in figure 12. Fig. 9. 8 Bit Multiplication in Xilinx Vivado The above results figure 8 and figure 9 shows the two bit decimal multiplayer that is it consists of 8 bits of binary digits which is simulated in Xilinx Vivado design suite Fig. 12. Performance difference chart V. CONCLUSION In digital Systems, power and energy consumption are two important constraints, and multiplication is the one tool that generally utilizes math modules. The prior parallel decimal works multiplication focuses on two major factors: Fig. 10. 16 Bit Multiplication in Xilinx Vivado delay and area of these math modules, and proposes possible solutions. In this research, we present a prediction-based The above results figure 10 simulated for 4 bit low- compared to the previously generated results. To reduce decimal integers so that we will be having 16 bits of binary power addition strategy for increasing the decimal digits and the results are generated in Xilinx Vivado Design multiplication uses a lot of energy/power and demonstrated suite and figure 11 for 32 bit multiplication. how it affected multiplier architecture13. The trial results suggest an 11.5 percent boost in terms of effectiveness 10.13 percent improvement in overall power consumption in terms of energy usage. An efficient algorithm can be implemented further to reduce power and delay. REFERENCES [1] Muralidharan, V., and N. Sathish Kumar. "Design and implementation of low power and high speed multiplier using quaternary carry look- ahead adder." Microprocessors and Microsystems 75 (2020): 103054. [2] Véstias, Mário P., and Horácio C. Neto. "Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor." Algorithms 14.7 (2021): 198. [3] Ghose, Debaprasad, Dharamvir Kumar, and Manoranjan Pradhan. "Comparative Analysis of Decimal Fixed-Point Parallel Multipliers Using Signed Digit Radix-4, 5 and 10 Encodings." Recent Trends in Electronics and Communication. Springer, Singapore, 2022. 345-353. [4] Gorgin, Saeid, HeliaZareieNejad, and Jeong-A. Lee. "A Practical Energy/Power Reduction Approach for Parallel Decimal Multiplier." IEEE Access (2022). [5] Malekpour, Amin, Alireza Ejlali, and SaeidGorgin. "A comparative study of energy/power consumption in parallel decimal multipliers." Microelectronics Journal 45.6 (2018): 775-780. Fig. 11. 32 Bit Multiplication in Xilinx Vivado Authorized licensed use limited to: VIT University. Downloaded on September 25,2023 at 16:24:58 UTC from IEEE Xplore. Restrictions apply. [6] P.L. Thangkhiew, R. Gharpinde, P.V. Chowdhary, K. Datta, I. Sengupta, Area efficient implementation of ripple carry adder using memristor crossbar arrays, in: 2016 11th International Design & Test Symposium (IDT), IEEE, 2016, December, pp. 142–147. [7] J. Barman, V. Kumar, Approximate carry look ahead adder (CLA) for error tolerant applications, in: 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI), IEEE, 2018, May, pp. 730–734. [8] R.A. Javali, R.J. Nayak, A.M. Mhetar, M.C. Lakkannavar, Design of high speed carry save adder using carry lookahead adder, in: International Conference on Circuits, Communication, Control and Computing, IEEE, 2014, November, pp. 33–36. [9] P. Devi, A. Girdher, B. Singh, Improved carry select adder with reduced area and low power consumption, Int. J. Comput. Appl. 3 (4) (June 2010) 14–18. [10] J. Ramasamy, N.S. Kumar, B. Sivasankari, Approximate carry select adder based multiplierless multiplication (AMLM), Middle-East J. Sci. Res. 24 (9) (2016) 2772 –2777. [11] Afreen, N. Fahmina, M. Mahaboob Basha, and S. Mohan Das. "Design and implementation of area-delay-power efficient CSLA based 32-bit array multiplier." 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT). IEEE, 2017. [12] J. Kaur, L. Sood, Comparison between various types of adder topologies, IJCST 6 (1) (2015) 62–66. [13] P. Paliwal, J.B. Sharma, V. Nath, Comparative study of FFA architectures using different multiplier and adder topologies, Microsyst. Technol. (2019) 1–8. [14] B. Ramkumar and H.M. Kittur, “Low-power and area efficient carry select adder” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 371–375, Feb. 2012. [15] M. NeelaSupraja, M. Mahaboob Basha “Low area Energy efficient Carry select Adder at 65nm technology,” ICRAESIT., ISBN:978-93- 85100-47-5, Dec-2015. [16] Silparaj.P, Punitha.V, “Design of Improved Array Multiplier by Carry Select Logic”, IJRASET, ISSN: 2321-9653, vol. 3, issue 4, April- 2015. [17] J. Barman, V. Kumar, Approximate carry look ahead adder (CLA) for error tolerant applications, in: 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI), IEEE, 2018, May, pp. 730–734. [18] S. Gorgin, G. Jaberipur, and B. Parhami, ‘‘Design and evaluation of decimal array multipliers,’’ in Proc. 43th Asilomar Signals, Syst., Comput., 2009, pp. 1782–1786. [19] L. Han and S.-B. Ko, ‘‘High-speed parallel decimal multiplication with redundant internal encodings,’’ IEEE Trans. Comput., vol. 62, no. 5, pp. 956–968, May 2013. [20] M. de la GuiaSolaz and R. Conway, Comparative study on word length reduction and truncation for low power multipliers, in: Proceedings of the 33rd International Convention Mipro 2010, pp. 84–88. [21] B. Kayalvizhi, N. Anies Fathima and T. Kavitha “Booth Recoded Wallace Tree Multiplier Using and Based Digitally Controlled Delay Lines” ARPN Journal of Engineering and Applied Sciences, pp, 2707- 2713, vol. 10, no. 6, April2015. Authorized licensed use limited to: VIT University. Downloaded on September 25,2023 at 16:24:58 UTC from IEEE Xplore. Restrictions apply.