IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A JSON library implemented in VHDL.

Portable HyperRAM controller

Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

APB Interfacing logic for Propell

The FPGA-Based FIFO