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1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2655,6 +2655,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FLOG10:
case ISD::FNEARBYINT:
case ISD::FNEG:
case ISD::FREEZE:
case ISD::FRINT:
case ISD::FROUND:
case ISD::FROUNDEVEN:
Expand Down
15 changes: 15 additions & 0 deletions llvm/test/CodeGen/LoongArch/fp16-promote.ll
Original file line number Diff line number Diff line change
Expand Up @@ -324,3 +324,18 @@ define void @test_fmul_mem(ptr %p, ptr %q) nounwind {
store half %r, ptr %p
ret void
}

define half @freeze_half() nounwind {
; LA32-LABEL: freeze_half:
; LA32: # %bb.0:
; LA32-NEXT: fadd.s $fa0, $fa0, $fa0
; LA32-NEXT: ret
;
; LA64-LABEL: freeze_half:
; LA64: # %bb.0:
; LA64-NEXT: fadd.s $fa0, $fa0, $fa0
; LA64-NEXT: ret
%y1 = freeze half undef
%t1 = fadd half %y1, %y1
ret half %t1
}
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