Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.

BookSim 2.0

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

《互联网络原理与实践（中文翻译）》Principles and Practices of Interconnection Networks

Free ChatGPT&DeepSeek API Key，免费ChatGPT&DeepSeek API。免费接入DeepSeek API和GPT4 API，支持 gpt | deepseek | claude | gemini | grok 等排名靠前的常用大模型。

Playing around with Thrift using Python, C#, and C++

RISC-V Instruction Set Manual

A functioning gem5 model of a neural-net based branch predictor, benchmarked as branch predictor for a 5-stage Sparc processor versus the default branch predictor.

A C version of Branch Predictor Simulator

SystemVerilog implemention of the TAGE branch predictor

64KB branch predictor using TAGE

Implementation of TAGE Branch Predictor - currently considered state of the art

TVM for chips base on Xuantie CPU, an open deep learning compiler stack.

RISC-V CPU Core (RV32IM)

compiler learning resources collect.

Open Machine Learning Compiler Framework

code reading for tvm

OpenMMLab Pre-training Toolbox and Benchmark

mflowgen -- A Modular ASIC/FPGA Flow Generator

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SGAS: Sequential Greedy Architecture Search (CVPR'2020) https://www.deepgcns.org/auto/sgas

上海交通大学 LaTeX 论文模板 | Shanghai Jiao Tong University LaTeX Thesis Template

Python-based Hardware Design Processing Toolkit for Verilog HDL